1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and apparatus that tests a register-readiness condition to improve the performance of value prediction.
2. Related Art
In the competitive marketplace for microprocessors, processor designers are forced to produce generation after generation of processors that continually improve in performance. As they stretch performance limits, processor designers face significant hurdles in achieving additional performance gains. In many instances, simply using improved circuitry or better fabrication processes to wring more performance from a processor design is impractical. Consequently, designers have relied on many different techniques to extract the maximum processor performance.
One such technique to improve performance involves altering program code to support “value prediction.” In a program that supports value prediction, the result of qualifying functions is stored (along with the inputs that lead to the result). When a call to the qualifying function is encountered, the program checks to see if a result was previously computed with the same input. If so, the program uses the previously computed result instead of re-executing the function. In this way, the program avoids re-computing a result for the function for the same input value.
Unfortunately, the usefulness of this type of value prediction is limited because the lookup for the previously computed result may take a significant amount of time. For example, if the lookup causes an L1 cache miss, the processor may have to wait for the previously computed result to return from L2 cache or main memory before the lookup completes. Because the latency of a return from L2 cache or main memory can be dozens or hundreds of cycles, the lookup can be quite time-consuming. Consequently, the use of this technique has been limited to only the largest of functions.
Hence, what is needed is a method and apparatus for performing value prediction without the above-described problems.